1. Field of the Invention
The present invention relates to a frequency modulation circuit and, more particularly, to a frequency modulation circuit in which an integrated mono-stable multi-vibrator and an emitter-follower connection transistor driven by a high power supply voltage are used, and the influence of a variation in frequency caused by noise is reduced.
2. Description of the Related Art
As a conventional mono-stable multi-vibrator circuit, a circuit constituted by an integrated mono-stable multi-vibrator is known.
Here, FIG. 4A is a view showing an arrangement of an integrated mono-stable multi-vibrator used in a known mono-stable multi-vibrator circuit, and FIG. 4B is a truth table obtained when the integrated mono-stable multi-vibrator operates.
This integrated mono-stable multi-vibrator 30 is constituted by a very-high-speed CMOS mono-stable multi-vibrator using a silicon gate CMOS technique. In the integrated mono-stable multi-vibrator 30, first and second basic circuits 31 and 32 having the same circuit arrangements are parallelly arranged to be connected to each other. The mono-stable multi-vibrator is available from Toshiba Corp. as model number TC74VHC123AF/AFS or TC74VHC221AF/AFS.
As shown in FIG. 4A, in the integrated mono-stable multi-vibrator 30, the first basic circuit 31 has an inversion trigger terminal 1(A*), a non-inversion trigger terminal 1B, an inversion clear terminal 1(CLR*), a resistor/capacitor terminal 1R.sub.X /C.sub.X, a capacitor terminal 1C.sub.X, and complementary output terminals 1(Q*) and 1Q; and the second basic circuit 32 has an inversion trigger terminal 2(A*), a non-inversion trigger terminal 2B, an inversion clear terminal 2(CLR*), a resistor/capacitor terminal 2R.sub.X /C.sub.X, a capacitor terminal 2C.sub.X, and complementary output terminals 2(Q*) and 2Q. In addition, although not shown in FIG. 3, the integrated mono-stable multi-vibrator 30 has a power supply terminal V.sub.CC and a ground terminal GND which are shared by the first and second basic circuits 31 and 32.
Note that, of the numerical symbols added to the respective terminals of the integrated mono-stable multi-vibrator 30, a numerical symbol with brackets and mark * represents that an inversion sign is added to the symbol in the brackets. In the following description, when symbols added to respective constituent elements have inversion signs, these symbols are represented in the same manner as described above.
The first and second basic circuits 31 and 32 are triggered when the fall edge of a trigger input is applied to the inversion trigger terminal 1(A*) and the inversion trigger terminal 2(A*). On the other hand, the first and second basic circuits 31 and 32 are triggered when the rise edge of a trigger input is applied to the non-inversion trigger terminal 1B and the non-inversion trigger terminal 2B. The trigger inputs applied to the inversion trigger terminal 1(A*) and the non-inversion trigger terminal 1B and the trigger inputs applied to the inversion trigger terminal 2(A*) and the non-inversion trigger terminal 2B constitute schmidt trigger inputs.
FIG. 5 is a view showing an arrangement of a main part of a mono-stable multi-vibrator circuit constituted by the first basic circuit 31 or the second basic circuit 32 of the integrated mono-stable multi-vibrator 30 shown in FIG. 4A. FIG. 6 is a waveform chart showing changes in signal of the respective portions when the mono-stable multi-vibrator circuit shown in FIG. 5 operates.
In this case, referring to FIG. 5, the mono-stable multi-vibrators constituted by the first basic circuit 31 and the second basic circuit 32 have the same circuit arrangements. For this reason, only the portion of the mono-stable multi-vibrator circuit using the first basic circuit 31 is illustrated, and the second basic circuit 32 is omitted in FIG. 5. The same reference numerals as in FIG. 4 denote the same parts in FIG. 5. However, with respect to numerical symbols added to the respective terminals of the first basic circuit 31, number 1 representing the first basic circuit 31 is omitted, and the terminals are represented by only the symbols.
As shown in FIG. 5, in the first basic circuit 31 of the integrated mono-stable multi-vibrator 30, a resistor 33 and a diode 33D (if necessary) are connected between the resistor/capacitor terminal R.sub.X /C.sub.X and the power supply V.sub.CC, and a capacitor 34 is connected between the resistor/capacitor terminal R.sub.X /C.sub.X and the capacitor terminal C.sub.X, thereby constituting a mono-stable multi-vibrator circuit as a whole.
The operation of the mono-stable multi-vibrator circuit with the above arrangement will be described below with reference to FIG. 6.
In a period between time t.sub.0 and t.sub.1, when the inversion trigger terminal 1(A*) and the non-inversion trigger terminal 1B are at low level (L) and high level (H), respectively, the resistor/capacitor terminal R.sub.X /C.sub.X is set in a high-impedance state. For this reason, the power supply terminal V.sub.CC is applied to the circuit, and the complementary output terminal Q and the complementary output terminal (Q*) are at low level (L) and high level (H), respectively.
At time t.sub.1, when the rise edge of a trigger input is supplied to the non-inversion trigger terminal B, the resistor/capacitor terminal R.sub.X /C.sub.X shifts to a low-impedance state, and a voltage sharply drops from the power supply terminal V.sub.CC. At this time, the complementary output terminal Q and the complementary output terminal (Q*) shift to high level (H) and low level (L), respectively.
When it is time t.sub.1 ', and the voltage of the resistor/capacitor terminal R.sub.X /C.sub.X gradually decreases to exceed a low-voltage-side set voltage VrefL which is set in the first basic circuit 31 in advance, the resistor/capacitor terminal R.sub.X /C.sub.X shifts to the high-impedance state again. As a result, the voltage gradually increases by a CR time constant determined by the resistor 33 and the capacitor 34.
At time t.sub.2, when the voltage of the resistor/capacitor terminal R.sub.X /C.sub.X gradually increases to reach a high-voltage-side reference voltage VrefH which is set in the first basic circuit 31 in advance, the complementary output terminal Q and the complementary output terminal (Q*) shift to low level (L) and high level (H), respectively. However, the voltage of the resistor/capacitor terminal R.sub.X /C.sub.X continuously increases by the CR time constant determined by the resistor 33 and the capacitor 34 subsequently.
At time t.sub.3 ', when the fall edge of a trigger input is supplied to the inversion trigger terminal (A*), the resistor/capacitor terminal R.sub.X /C.sub.X shifts to a low-impedance state, and the voltage sharply decreases. At this time, the complementary output terminal Q and the complementary output terminal (Q*) also shift to high level (H) and low level (L), respectively.
When it is time t.sub.3 ', the voltage of the resistor/capacitor terminal R.sub.X /C.sub.X gradually decreases to exceed the low-voltage-side reference voltage VrefL, the resistor/capacitor terminal R.sub.X /C.sub.X shifts to a high-impedance state as in the case described above, and the voltage gradually increases by the CR time constant determined by the resistor 33 and the capacitor 34.
At time t.sub.4, when the voltage resistor/capacitor terminal R.sub.X /C.sub.X gradually increases to reach a high-voltage-side reference voltage VrefH, the complementary output terminal Q and the complementary output terminal (Q*) shift to low level (L) and high level (H), respectively. The voltage of the resistor/capacitor terminal 1R.sub.X /C.sub.X continuously increases by the CR time constant determined by the resistor 33 and the capacitor 34.
At time t.sub.5, when the fall edge of a trigger input is supplied to the inversion trigger terminal (A*), the same operation as that performed at time t.sub.3 described above is executed. Thereafter, the same operation as that at time t.sub.3 ' described above is executed, and the same operation as described above is repetitively executed.
When the above operations are executed, a mono-stable signal of a negative polarity which is kept in only a period t.sub.w out can be output from the complementary output terminal (Q*).
Subsequently, FIG. 7 is a circuit diagram showing a known frequency modulation circuit constituted by the mono-stable multi-vibrator circuit shown in FIG. 5. The same reference numerals as in FIG. 5 denote the same parts in FIG. 7.
As shown in FIG. 7, the frequency modulation circuit is constituted in such a manner that an emitter-follower connection transistor 35 is coupled to the integrated mono-stable multi-vibrator 30. The transistor 35 has: a base connected to a modulation signal source 37 through a coupling capacitor 36 and connected to base-bias resistors 38 and 39; a collector directly grounded; and an emitter connected to a power supply terminal 41 through an emitter resistor 40. In the integrated mono-stable multi-vibrator 30, the resistor/capacitor terminal R.sub.X /C.sub.X is connected to the emitter of the transistor 35 through the resistor 33 and connected to a capacitor terminal C.sub.X through the capacitor 34, the inversion trigger terminal (A*) is connected to the complementary output terminal Q, and the non-inversion trigger terminal B is connected to the voltage setting resistors 42 and 43 and a bypass capacitor 44. The inversion clear terminal (CLR*) and the power supply terminal V.sub.CC are connected to the power supply terminal 41, and the capacitor terminal C.sub.X is grounded. A D flip-flop 45 has: a clock terminal C.sub.K connected to the complementary output terminal (Q*) of the integrated mono-stable multi-vibrator 30; a delay terminal D connected to the complementary output terminal (Q*); and a complementary output terminal Q connected to a signal output terminal 46.
The frequency modulation circuit with the above arrangement operates in the following manner.
When a modulation signal is supplied from the modulation signal source 37 to the base of the emitter-follower connection transistor 35 through the coupling capacitor 36, the modulation signal is current-amplified by the transistor 35, and a voltage (to be referred to as a modulation signal dependent voltage hereinafter) which is proportional to the level of the modulation signal is generated by the emitter of the transistor 35. The modulation signal level dependent voltage is applied to the resistor/capacitor terminal R.sub.X /C.sub.X (in a high-impedance state) of the integrated mono-stable multi-vibrator 30 through the resistor 33. In the integrated mono-stable multi-vibrator 30, a logic level H depending on the partial voltage ratio of the voltage setting resistor 42 to the voltage setting resistor 43 is applied to the non-inversion trigger terminal B. When the modulation signal dependent voltage is supplied from the transistor 35, the voltage of the resistor/capacitor terminal R.sub.X /C.sub.X set in a high-impedance state gradually increases by a charge time constant of the modulation signal dependent voltage determined by the resistor 33 and the capacitor 34. At this time, the complementary output terminal Q and the complementary output terminal (Q*) are at high level (H) and low level (L), respectively.
Here, when the voltage of the resistor/capacitor terminal R.sub.X /C.sub.X gradually increases to reach a set voltage VrefH (this set voltage VrefH is set by a power supply voltage and the integrated mono-stable multi-vibrator 30) applied to the non-inversion trigger terminal B, the state of the resistor/capacitor terminal R.sub.X /C.sub.X is converted into a low-impedance state, and the voltage of the resistor/capacitor terminal R.sub.X /C.sub.X sharply decreases. In addition, the level of the complementary output terminal Q is converted from high level (H) to low level (L), and the level of the complementary output terminal (Q*) is converted from low level (L) into high level (H).
When the voltage of the resistor/capacitor terminal R.sub.X /C.sub.X decreases to the low-voltage-side set voltage (low-voltage-side reference voltage) VrefL equal to a low-level (L) voltage applied from the complementary output terminal Q to the inversion trigger terminal (A*), the state of the resistor/capacitor terminal R.sub.X /C.sub.X is converted into a high-impedance state, and the voltage of the resistor/capacitor terminal R.sub.X /C.sub.X gradually increases by a charge time constant of a modulation signal dependent voltage determined by the resistor 33 and the capacitor 34. In addition, the level of the complementary output terminal Q is converted from low level (L) into high level (H), and the level of the complementary output terminal (Q*) is converted from high level (H) into low level (L).
Thereafter, when the voltage of the resistor/capacitor terminal R.sub.X /C.sub.X reaches the high-voltage-side set voltage VrefH, the voltage begins to sharply decrease, and the polarities of the levels of the complementary output terminal Q and the complementary output terminal (Q*) are inverted. Subsequently, when the voltage of the resistor/capacitor terminal R.sub.X /C.sub.X reaches a low-voltage-side set voltage VrefL, the voltage gradually increases by a charge time constant determined by the resistor 33 and the capacitor 34. The operation that the polarities of the levels of the complementary output terminal Q and the complementary output terminal (Q*) are inverted again is repetitively executed.
The D flip-flop 45 is triggered by the rise edge of a pulse supplied from the complementary output terminal (Q*), and a pulse whose polarity is inverted each time the D flip-flop 45 is triggered by the rise edge of an input pulse from the complementary output terminal Q is supplied to the signal output terminal 46.
In this case, since the voltage of the resistor/capacitor terminal R.sub.X /C.sub.X gradually increases by the charge time constant of the modulation signal dependent voltage determined by the resistor 33 and the capacitor 34, a time until the voltage of the resistor/capacitor terminal R.sub.X /C.sub.X reaches the high-voltage-side set voltage VrefH is short when the modulation signal dependent voltage is high, a low-level (L) period of time of a pulse output from the complementary output terminal (Q*) becomes short. On the other hand, a time until the voltage of the resistor/capacitor terminal R.sub.X /C.sub.X reaches the high-voltage-side set voltage VrefH is long when the modulation signal dependent voltage, and a low-level (L) period of a pulse output from the complementary output terminal (Q*) becomes long. A pulse output from the complementary output terminal Q of the D flip-flop 45 becomes a signal frequency-converted by the modulation voltage of the modulation signal source 37.
In the above known frequency modulation circuit, when the voltage of the resistor/capacitor terminal R.sub.X /C.sub.X gradually increases by the charge time constant of a modulation signal dependent voltage determined by the resistor 33 and the capacitor 34 to reach a high-voltage-side set voltage VrefH, the level of a pulse output from the complementary output terminal (Q*) is converted from low level (L) into high level (H), and the conversion timing is dependent on the modulation signal level. For this reason, a pulse signal frequency-modulated by a modulation signal can be extracted from the complementary output terminal (Q*). However, since the high-voltage-side set voltage VrefH is set by a power supply voltage and the characteristics of the integrated mono-stable multi-vibrator 30, induction noise may be superposed on the high-voltage-side set voltage VrefH.
In the known frequency modulation circuit, when induction noise is superposed on the high-voltage-side set voltage VrefH, the level of the high-voltage-side set voltage VrefH varies depending on the polarity and level of the induction noise. For this reason, the timing at which the gradually increasing voltage of the resistor/capacitor terminal R.sub.X /C.sub.X reaches the high-voltage-side set voltage VrefH varies depending on the polarity and level of the induction noise. As a result, a timing at which the level of a pulse output from the complementary output terminal (Q*) is converted from low level (L) into high level (H) also varies depending on the polarity of and level of the induction noise, and a pulse signal which is correctly frequency-modulated by the modulation signal cannot be extracted disadvantageously.